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preliminary technical data preliminary technical data rev. prd ADG3247 2.5 v/3.3 v, 16-bit, 2-port level translating, bus switch information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. features 225 ps propagation delay through the switch 4.5 switch connection between ports data rate 1.244 gbps 2.5 v/3.3 v supply operation selectable level shifting/translation small signal bandwidth 610 mhz level translation 3.3 v to 2.5 v 3.3 v to 1.8 v 2.5 v to 1.8 v 40-lead 6 mm 6 mm lfcsp and 38-lead tssop packages applications 3.3 v to 1.8 v voltage translation 3.3 v to 2.5 v voltage translation 2.5 v to 1.8 v voltage translation bus switching bus isolation hot plug hot swap analog switching applications functional block diagram a7 b7 be1 a0 b0 a15 b15 be2 a8 b8 general description the ADG3247 is a 2.5 v or 3.3 v 16-bit, 2-port digital switch. it is designed on analog devices?low voltage cmos process, which provides low power dissipation yet gives high switching speed and very low on resistance, allowing inputs to be connected to outputs without additional propagation delay or generating additional ground bounce noise. the ADG3247 is organized as dual 8-bit bus switches with separate bus enable ( bex ) inputs. this allows the device to be used as two 8-bit digital switches or one 16-bit bus switch. these bus switches allow bidirectional signals to be switched when on. in the off condition, signal levels up to the supplies are blocked. this device is ideal for applications requiring level translation. when operated from a 3.3 v supply, level translation from 3.3 v inputs to 2.5 v outputs occurs. similarly, if the device is operated from a 2.5 v supply and 2.5 v inputs are applied, the device will translate the outputs to 1.8 v. in addition to this, the ADG3247 has a level translating select pin ( sel ). when sel is low, v cc is reduced internally, allowing for level translation between 3.3 v inputs and 1.8 v outputs. this makes the device suited to appli- cations requiring level translation between different supplies, such as converter to dsp/microcontroller interfacing. product highlights 1. 3.3 v or 2.5 v supply operation 2. extremely low propagation delay through switch 3. 4.5 ? switches connect inputs to outputs 4. level/voltage translation 5. 40-lead 6 mm 6 mm lfcsp and 38-lead tssop packages
preliminary technical data rev. prd ? ADG3247?pecifications 1 (v cc = 2.3 v to 3.6 v, gnd = 0 v, all specifications t min to t max , unless otherwise noted.) b version parameter symbol conditions min typ 2 max unit dc electrical characteristics input high voltage v inh v cc = 2.7 v to 3.6 v 2.0 v v inh v cc = 2.3 v to 2.7 v 1.7 v input low voltage v inl v cc = 2.7 v to 3.6 v 0.8 v v inl v cc = 2.3 v to 2.7 v 0.7 v input leakage current i i 0.01 1 a off state leakage current i oz 0 a, b v cc 0.01 1 a on state leakage current i ol 0 a, b v cc 0.01 1 a max pass voltage v p v a /v b = v cc = sel = 3.3 v, i o = ? a 2.0 2.5 2.9 v v a /v b = v cc = sel = 2.5 v, i o = ? a 1.5 1.8 2.1 v v a /v b = v cc = 3.3 v, sel = 0 v, i o = ? a 1.5 1.8 2.1 v capacitance 3 a port off capacitance c a off f = 1 mhz 5 pf b port off capacitance c b off f = 1 mhz 5 pf a, b port on capacitance c a , c b on f = 1 mhz 10 pf control input capacitance c in f = 1 mhz 6 pf switching characteristics 3 propagation delay a to b or b to a, t pd 4 t phl, t plh c l = 50 pf, v cc = sel = 3 v 0.225 ns propagation delay matching 5 22.5 ps bus enable time bex to a or b 6 t pzh , t pzl v cc = 3.0 v to 3.6 v; sel = v cc 1 3.2 4.8 ns bus disable time bex to a or b 6 t phz , t plz v cc = 3.0 v to 3.6 v; sel = v cc 1 3.2 4.8 ns bus enable time bex to a or b 6 t pzh , t pzl v cc = 3.0 v to 3.6 v; sel = 0 v 0.5 2.2 3.3 ns bus disable time bex to a or b 6 t phz , t plz v cc = 3.0 v to 3.6 v; sel = 0 v 0.5 1.7 2.9 ns bus enable time bex to a or b 6 t pzh , t pzl v cc = 2.3 v to 2.7 v; sel = v cc 0.5 2.2 3 ns bus disable time bex to a or b 6 t phz , t plz v cc = 2.3 v to 2.7 v; sel = v cc 0.5 1.75 2.6 ns max data rate v cc = sel = 3.3 v; v a /v b = 2 v 1.244 gbps channel jitter v cc = sel = 3.3 v; v a /v b = 2 v 50 ps p-p operating frequency?us enable f bex 10 mhz digital switch on resistance r on v cc = 3 v, sel = v cc , v a = 0 v, i ba = 8 ma 4.5 8 ? v cc = 3 v, sel = v cc , v a = 1.7 v, i ba = 8 ma 15 28 ? v cc = 2.3 v, sel = v cc , v a = 0 v, i ba = 8 ma 59 ? v cc = 2.3 v, sel = v cc , v a = 1 v, i ba = 8 ma 11 18 ? v cc = 3 v, sel = 0 v, v a = 0 v, i ba = 8 ma 58 ? v cc = 3 v, sel = 0 v, v a = 1 v, i ba = 8 ma 14 ? on resistance matching ? r on v cc = 3 v, sel = v cc , v a = 0 v, i ba = 8 ma 0.45 ? v cc = 3 v, sel = v cc , v a = 1 v, i ba = 8 ma 0.65 ? power requirements v cc 2.3 3.6 v quiescent power supply current i cc digital inputs = 0 v or v cc ; sel = v cc 0.001 1 a i cc digital inputs = 0 v or v cc ; sel = 0 v 0.65 1.2 ma increase in i cc per input 7 ? i cc v cc = 3.6 v, be 1 = 3.0 v; be 2 = v cc or gnd; sel = v cc 85 a notes 1 temperature range is as follows: b version: ?0 c to +85 c. 2 typical values are at 25 c, unless otherwise stated. 3 guaranteed by design, not subject to production test. 4 the digital switch contributes no propagation delay other than the rc delay of the typical r on of the switch and the load capacitance when driven by an ideal voltage source. since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propag ation delay to the system. propagation delay of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its inte raction with the load on the driven side. 5 propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pf. 6 see timing measurement information. 7 this current applies to the control pins ( bex ) only. the a and b ports contribute no significant ac or dc currents as they transition. specifications subject to change without notice.
preliminary technical data rev. prd ADG3247 ? absolute maximum ratings * (t a = 25 c, unless otherwise noted.) v cc to gnd . . . . . . . . . . . . . . . . . . . . . . . . . ?.5 v to +4.6 v digital inputs to gnd . . . . . . . . . . . . . . . . . ?.5 v to +4.6 v dc input voltage . . . . . . . . . . . . . . . . . . . . . ?.5 v to +4.6 v dc output current . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 ma operating temperature range industrial (b version) . . . . . . . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c lfcsp package ja thermal impedance . . . . . . . . . . . . . . . . . . . . . . . 32 c/w tssop package ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 98 c/w lead temperature, soldering (10 seconds) . . . . . . . . . . 300 c ir reflow, peak temperature (<20 seconds) . . . . . . . . 235 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADG3247 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. table i. pin description mnemonic description bex bus enable (active low) sel level translation select ax port a, inputs or outputs bx port b, inputs or outputs table ii. truth table bex sel * function ll a = b, 3.3 v to 1.8 v level shifting lh a = b, 3.3 v to 2.5 v/2.5v to 1.8 v level shifting hx disconnect * sel = 0 only when v dd = 3.3 v 10% pin configuration 40-lead lfcsp and 38-lead tssop pin 1 indicator top view ADG3247 1 a6 2 a7 3 a8 4 a9 5 a10 6 a11 7 a12 8 a13 9 a14 10 a15 nc = no connect gnd 11 nc 12 nc 13 nc 14 b15 15 b14 16 b13 17 b12 18 b11 19 b10 20 30 b0 29 b1 28 b2 27 b3 26 b4 25 b5 24 b6 23 b7 22 b8 21 b9 40 a5 39 a4 38 a3 37 a2 36 a1 35 a0 34 sel 33 vcc 32 be2 31 be1 top view (not to scale) 38 37 36 35 34 33 32 1 2 3 4 5 6 7 sel a0 a1 a2 a3 a4 a5 v cc be2 be1 b0 b1 b2 b3 ADG3247 31 30 29 8 9 10 a6 a7 a8 b4 b5 b6 28 27 11 12 a9 a10 b7 b8 26 25 a11 a12 b9 b10 24 23 22 17 a13 a14 a15 b11 b12 b13 21 20 18 19 gnd nc b14 b15 13 14 15 16 ordering guide model temperature range package description package option ADG3247bcp ?0 c to +85 cl eaded chip scale package (lfcsp) cp-40 ADG3247bru ?0 c to +85 ct hin shrink small outline package (tssop) ru-38
preliminary technical data rev. prd ADG3247 ? terminology v cc positive power supply voltage gnd ground (0 v) reference v inh minimum input voltage for logic 1 v inl maximum input voltage for logic 0 i i input leakage current at the control inputs i oz off state leakage current. it is the maximum leakage current at the switch pin in the off state. i ol on state leakage current. it is the maximum leakage current at the switch pin in the on state. v p max pass voltage. the max pass voltage relates to the clamped output voltage of an nmos device when the switch input voltage is equal to the supply voltage. r on ohmic resistance offered by a switch in the on state. it is measured at a given voltage by forcing a specified amount of current through the switch. r on on resistance match between any two channels, i.e., r on max ?r on min c x off off switch capacitance c x on on switch capacitance c in control input capacitance. this consists of bex and sel . i cc quiescent power supply current. it is measured when all control inputs are at a logic high or low level and the switches are off. i cc extra power supply current component per each bex control input when the input is not driven at the supplies. t plh , t phl data propagation delay through the switch in the on state. propagation delay is related to the rc time constant r on c l , where c l is the load capacitance. t pzh , t pzl bus enable times. these are the times taken to cross the v t voltage at the switch output when the switch turns on in response to the control signal, bex . t phz , t plz bus disable times. these are the times taken to place the switch in the high impedance off state in response to the control signal. they are measured as the time taken for the output voltage to change by v from the original quiescent level, with reference to the logic level transition at the control input. (refer to figure 3 for enable and disable times.) max data rate maximum rate at which data can be passed through the switch channel jitter peak-to-peak value of the sum of the deterministic and random jitter of the switch channel f be operating frequency of bus enable. this is the maximum frequency at which bus enable (be) can be toggled.
preliminary technical data rev. prd t ypical performance characteristics?dg3247 ? v a /v b ?v r on 0 0 0.5 t a = 25 c sel = v cc 5 10 15 20 25 30 35 40 1.5 2.5 3.5 v cc = 3v v cc = 3.3v v cc = 3.6v 3.0 2.0 1.0 tpc 1. on resistance vs. input voltage v a /v b ?v r on 0 0 0.5 5 10 15 20 1.5 2.0 1.0 25 c 85 c 40 c = 3.3v sel = v cc v cc tpc 4. on resistance vs. input voltage for different temperatures v cc ?v v out ?v 0 0 0.5 0.5 1.5 2.5 1.5 2.5 v cc = 2.7v v cc = 2.5v v cc = 2.3v t a = 25 c sel = v cc i o = ? a 2.0 1.0 1.0 2.0 3.0 tpc 7. pass voltage vs. v cc v a /v b ?v r on 0 0 0.5 5 10 15 20 25 30 35 40 1.5 2.5 v cc = 2.3v v cc = 2.5v v cc = 2.7v t a = 25 c sel = v cc 3.0 2.0 1.0 tpc 2. on resistance vs. input voltage v a /v b ?v r on 0 00.5 5 10 15 85 c 25 c 1.0 40 c = 2.5v sel = v cc v cc 1.2 tpc 5. on resistance vs. input voltage for different temperatures v cc ?v v out ?v 0 0 0.5 0.5 1.5 2.5 1.5 2.5 v cc = 3.6v v cc = 3.3v v cc = 3v 3.5 t a = 25 c sel = 0v i o = ? a 2.0 1.0 1.0 2.0 3.0 tpc 8. pass voltage vs. v cc v a /v b ?v r on 0 0 0.5 5 10 15 20 25 30 35 40 1.5 2.5 v cc = 3v v cc = 3.3v v cc = 3.6v 3.5 t a = 25 c sel = 0v 1.0 2.0 3.0 tpc 3. on resistance vs. input voltage v cc ?v v out ?v 0 0 0.5 0.5 1.5 2.5 1.5 2.5 3.5 v cc = 3.6v v cc = 3.3v v cc = 3v 3.0 2.0 1.0 1.0 2.0 3.0 t a = 25 c sel = v cc i o = ? a tpc 6. pass voltage vs. v cc enable frequency ?mhz i cc a 0 02 4 200 6810 t a = 25 c 12 v cc = 3.3v, sel = 0v 14 16 18 20 400 600 800 1000 1200 1400 1600 1800 v cc = sel = 3.3v v cc = sel = 2.5v tpc 9. i cc vs. enable frequency
preliminary technical data rev. prd ADG3247 ? i o ?a v out ?v 0 0.01 0.5 1.0 1.5 2.0 2.5 3.0 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 0 v cc = 3.3v; sel = 0v v cc = sel = 3.3v v cc = sel = 2.5v t a = 25 c v a = 0v be = 0 tpc 10. output low characteristic frequency ?mhz a ttenuation ?db 0 0.03 0.1 1000 ? 110 100 ? ? ? ?0 ?2 t a = 25 c v cc = 3.3v/2.5v sel = v cc v in = 0dbm n/w analyzer : r l = r s = 50 ?4 tpc 13. bandwidth vs. frequency temperature ? c 0 ?0 0.5 1.5 2.5 3.5 ?0 0 20 40 60 80 100 enable disable enable disable v cc = sel = 3.3v v cc = 3.3v, sel = 0v 3.0 2.0 1.0 time ?ns tpc 16. enable/disable time vs. temperature i o ?a v out ?v 0 0.10 0.5 1.0 1.5 2.0 2.5 3.0 0 t a = 25 c v a = v cc be = 0 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 v cc = sel = 2.5v v cc = 3.3v; sel = 0v v cc = sel = 3.3v tpc 11. output high characteristic frequency ?mhz a ttenuation ?db 0.03 0.1 1000 110 100 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 t a = 25 c v cc = 3.3v/2.5v sel = v cc adjacent channels v in = 0dbm n/w analyzer : r l = r s = 50 tpc 14. crosstalk vs. frequency temperature ? c time ?ns 0 ?0 0.5 1.5 2.5 ?0 0 20 40 60 80 100 enable disable v cc = sel = 2.5v 2.0 1.0 tpc 17. enable/disable time vs. temperature v a /v b ?v q inj ?pc ?.0 0 0.5 ?.0 ?.2 1.5 2.5 ?.4 ?.6 ?.8 ?.2 ?.4 ?.8 1.0 2.0 3.0 ?.6 0 v cc = 3.3v v cc = 2.5v t a = 25 c sel = v cc on off c l = inf tpc 12. charge injection vs. source voltage frequency ?mhz a ttenuation ?db 0.03 0.1 1000 110 100 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 t a = 25 c v cc = 3.3v/2.5v sel = v cc v in = 0dbm n/w analyzer : r l = r s = 50 ?00 tpc 15. off isolation vs. frequency data rate ?gbps jitter ?ps 0.5 0.6 60 70 80 90 100 50 0.7 0.8 0.9 1.1 1.2 1.3 1.4 1.5 1.0 40 30 20 10 0 v cc = sel = 3.3v v in = 2v p-p 20db attenuation tpc 18. jitter vs. data rate; prbs 31
preliminary technical data rev. prd ADG3247 ? data rate ?gbps eye width ?% 0.5 0.6 60 70 80 85 90 95 100 % eye width = ((clock period jitter p-p)/clock period) 100% 75 65 55 50 0.7 0.8 0.9 1.1 1.2 1.3 1.4 1.5 1.0 v cc = sel = 3.3v v in = 2v p-p 20db attenuation tpc 19. eye width vs. data rate; prbs 31 50.1mv/div 50ps/div t a = 25 c 20db a ttenuation v cc = 3.3v sel = 3.3v v in = 2v p-p tpc 22. jitter @ 1.244 gbps, prbs 31 v cc = 3.3v sel = 3.3v v in = 2v p-p 20db a ttenuation t a = 25 c 35mv/div 100ps/div tpc 20. eye pattern; 1.244 gbps, v cc = 3.3 v, prbs 31 37mv/div 200ps/div v cc = 2.5v sel = 2.5v v in = 2v p-p 20db a ttenuation t a = 28 c tpc 21. eye pattern; 1 gbps, v cc = 2.5 v, prbs 31
preliminary technical data rev. prd ADG3247 ? v cc v in v out c l r l r l sw1 gnd open 2 v cc r t d.u.t. pulse generator notes pu lse generator for all pulses: t r 2.5ns, t f 2.5ns, fre quency 10mhz. c l includes board, stray, and load capacitances. r t is the termination resistor, should be equal to z out of the pulse generator. figure 1. load circuit switch input 0v t phl output v t v ih v h v t v l t plh figure 2. propagation delay for the following load circuit and waveforms, the notation that is used is v in and v out where: vv and v v or vv and v v in a out b in b out a == == test conditions symbol v cc = 3.3 v 0.3 v ( sel = v cc ) v cc = 2.5 v 0.2 v ( sel = v cc ) v cc = 3.3 v 0.3 v ( sel = 0 v) unit r l 500 500 500 ? v ? 300 150 150 mv c l 50 30 30 pf v t 1.5 0.9 0.9 v enable disable control input bex v in = 0v v in = v cc v out sw1 @ 2v cc v out sw1 @ gnd t plz t pzh t phz t pzl v t 0v v cc v t v h v h ? v l v l + v v cc 0v v t v inh 0v figure 3. enable and disable times timing measurement information table iii. switch position test s1 t plz , t pzl 2 v cc t phz , t pzh gnd
preliminary technical data rev. prd ADG3247 ? bus switch applications mixed voltage operation, level translation bus switches can be used to provide an ideal solution for inter- facing between mixed voltage systems. the ADG3247 is suitable for applications where voltage translation from 3.3 v technology to a lower voltage technology is needed. this device can translate from 3.3 v to 1.8 v, from 2.5 v to 1.8 v, or bidirectionally from 3.3 v directly to 2.5 v. figure 4 shows a block diagram of a typical application in which a user needs to interface between a 3.3 v adc and a 2.5 v micro- processor. the microprocessor may not have 3.3 v tolerant inputs; therefore placing the ADG3247 between the two devices allows the devices to communicate easily. the bus switch directly connects the two blocks, thus introducing minimal propagation delay, timing skew, or noise. 3.3v adc 2.5v 3.3v 2.5v microprocessor ADG3247 3.3v figure 4. level translation between a 3.3 v adc and a 2.5 v microprocessor 3.3 v to 2.5 v translation when v cc is 3.3 v ( sel = v cc ) and the input signal range is 0 v to v cc , the maximum output signal will be clamped to within a voltage threshold below the v cc supply. ADG3247 2.5v 2.5v 3.3v 2.5v 3.3v figure 5. 3.3 v to 2.5 v voltage translation, sel = v cc in this case, the output will be limited to 2.5 v, as shown in figure 6. v in 2.5v v out 0v 3.3v s witch input s witch ou tput 3.3v supply sel = 3.3v figure 6. 3.3 v to 2.5 v voltage translation, sel = v cc this device can be used for translation from 2.5 v to 3.3 v devices, and also between two 3.3 v devices. 2.5 v to 1.8 v translation when v cc is 2.5 v ( sel = v cc ) and the input signal range is 0 v to v cc , the maximum output sign al will, as b efore, be clam ped to within a voltage threshold below the v cc supply. ADG3247 1.8v 2.5v 2.5v figure 7. 2.5 v to 1.8 v voltage translation, sel = v cc in this case, the output will be limited to approximately 1.8 v, as shown in figure 7. v in 1.8v v out 0v 2.5v s witch input s witch ou tput 2.5v supply sel = 2.5v figure 8. 2.5 v to 1.8 v voltage translation, sel = v cc 3.3 v to 1.8 v translation the ADG3247 offers the option of interfacing between a 3.3 v device and a 1.8 v device. this is possible through use of the sel pin. sel pin: an active low control pin. sel activates internal circuitry in the ADG3247 that allows voltage translation between 3.3 v devices and 1.8 v devices. ADG3247 1.8v 3.3v 3.3v figure 9. 3.3 v to 1.8 v voltage translation, sel = 0 v when v cc is 3.3 v and the input signal range is 0 v to v cc , the maximum output signal will be clamped to 1.8 v, as shown in figure 9. to do this, the sel pin must be tied to logic 0. if sel is unused, it should be tied directly to v cc .
preliminary technical data rev. prd ADG3247 ?0 v in 1.8v v out 0v 3.3v s witch input s witch ou tput 3.3v supply sel = 0v figure 10. 3.3 v to 1.8 v voltage translation, sel = 0 v bus isolation a common requirement of bus architectures is low capacitance loading of the bus. such systems require bus bridge devices that extend the number of loads on the bus without exceeding the specifications. because the ADG3247 is designed specifically for applications that do not need drive yet require simple logic func- tions, it solves this requirement. the device isolates access to the bus, thus minimizing capacitance loading. bus/ backplane load a load c load b load d bus switch location figure 11. location of bus switched in a bus isolation application hot plug and hot swap isolation the ADG3247 is suitable for hot swap and hot plug applications. the output signal of the ADG3247 is limited to a voltage that is below the v cc supply, as shown in figures 6, 8, and 10. there- fore the switch acts like a buffer to take the impact from hot insertion, protecting vital and expensive chipsets from damage. in hot-plug applications, the system cannot be shutdown when new hardware is being added. to overcome this, a bus switch can be positioned on the backplane between the bus devices and the hot plug connectors. the bus switch is turned off during hot plug. figure 12 shows a typical example of this type of application. plug-in card (1) card i/o card i/o ram cpu plug-in card (2) ADG3247 ADG3247 figure 12. ADG3247 in a hot plug application there are many systems that require the ability to handle hot swapping, such as docking stations, pci boards for servers, and line cards for telecommunications switches. if the bus can be isolated prior to insertion or removal, then there is more control over the hot swap event. this isolation can be achieved using a bus switch. the bus switches are positioned on the hot swap card between the connector and the devices. during hot swap, the ground pin of the hot swap card must connect to the ground pin of the back plane before any other signal or power pins. analog switching bus switches can be used in many analog switching applications; for example, video graphics. bus switches can have lower on resistance, smaller on and off channel capacitance and thus improved frequency performance than their analog counterparts. the bus switch channel itself consisting solely of an nmos switch limits the operating voltage (see tpc 1 for a typical plot), but in many cases this does not present an issue. high impedance during power-up/power-down to ensure the high impedance state during power-up or power- down, bex should be tied to v cc through a pull-up resistor; the minimum value of the resistor is determined by the current- sinking capability of the driver. package and pinout the ADG3247 is packaged in both a small 38-lead tssop or a tiny 40-lead lfcsp package. the area of the tssop option is 62.7 mm 2 , while the area of the lfcsp option is 36 mm 2 . this leads to a 43% savings in board space when using the lfcsp package compared with the tssop package. this makes the lfcsp option an excellent choice for space-constrained applications. the ADG3247 in the tssop package offers a flowthrough pinout. the term flowthrough signifies that all the inputs are on opposite sides from the outputs. a flowthrough pinout simplifies the pcb layout.
preliminary technical data rev. prd ADG3247 ?1 outline dimensions 40-lead frame chip scale package [lfcsp] (cp-40) dimensions shown in millimeters 1 40 10 11 31 30 21 20 bottom view 4.25 3.70 sq 1.75 top view 6.00 bsc sq pin 1 indicator 5.75 bsc sq 12 max 0.30 0.23 0.18 0.20 ref seating plane 1.00 0.90 0.80 0.05 max 0.02 nom coplanarity 0.08 1.00 max 0.65 nom 4.50 ref 0.50 0.40 0.30 0.50 bsc pin 1 indicator 0.60 max 0.60 max compliant to jedec standards mo-220-vjjd-2 38-lead thin shrink small outline package [tssop] (ru-38) dimensions shown in millimeters 38 20 19 1 9.80 9.70 9.60 pin 1 seating plane 0.15 0.05 0.50 bsc 1.20 max 0.27 0.17 0.20 0.09 8 0 4.50 4.40 4.30 6.40 bsc 0.70 0.60 0.45 compliant to jedec standards mo-153bd-1 coplanarity 0.10
c03013??/03(prd) printed in u.s.a. ?2

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